In personal computers, the most common method of connecting a hard disc drive to a data bus is through the use of the industry standard AT-Attachment or ATA drive interface, which is used in millions of disc drives and systems worldwide.
The current state of the art for this interface limits hard disc data transfer rates to about 16.6 Megabytes per second. This limitation is due to the constraints caused by system compatibility requirements imposed by the ATA standard, which requires that new disk drives built to a new version of the ATA specification must be capable of working in systems produced under earlier versions of the standard.
All of the versions of the ATA standard define the electrical requirements and protocols necessary to transfer data between a disk drive and a host processor, or some other device, across a 40-pin cable. The standard also defines commands issuable over the interface and various status words pertaining to the interface and the status of devices participating in data transfers.
The first version of the ATA standard, herein referred to as ATA-1, defined the two primary methods of data transfer supported by all versions of the ATA interface:
1) Programmed Input/Output ("PlO"), a word by word data transfer between the host and the hard disk device; and PA1 2) Direct Memory Access ("DMA"), a method of bursting blocks of data across the bus under hardware control between a memory and the hard disk device, with minimal involvement from the microprocessor. PA1 1) the ATA physical interface uses low-cost, low-performance cabling for the data path and signal assignments on the cable are poorly arranged so that signals are often degraded during transmission; PA1 2) the input/output drivers employed by the standard electrical interface are derived from very old TTL technology not designed for signal transmission on a cable, which results in poor signal quality; and PA1 3) the interface protocol incorporates built-in read and write overhead, bus high-impedance times and limitations in speed-control protocols. PA1 (a) the device asserts a DMA request on the DMA request line at a first time; PA1 (b) the host asserts a DMA acknowledge on the DMA acknowledge line at a second time in response to the DMA request; PA1 (c) the host activates the data strobe at a third time, the third time being after the second time, the difference between the second and third times being long enough for a data word placed on the data bus at a fourth time between the second and third times to stabilize by the third time, the data strobe making a first transition at the third time and a second transition at a fifth time, the difference between the third and fifth times being long enough for a data word placed on the data bus at an sixth time between the third and fifth times to stabilize by the fifth time; PA1 (d) a sender selected from the host or the device places a first data word on the data bus at the fourth time, removes the first data word after the third time, and, without placing the data bus in a high impedance state, places a second data word on the data bus at the sixth time; and PA1 (e) a receiver selected from the one of the host or the device not being the sender inputs reads the first and second data words from the data bus at the third and fifth times respectively. PA1 (a) the sender accumulates each of the data words placed on the data lines into a send checksum; PA1 (b) the receiver accumulates each of the data words received from the data lines into a receive checksum; PA1 (c) after sending the last data word of the data block, the sender places the send checksum on the data lines after a last high to low transition of the data strobe and before the host deasserts the DMA acknowledge; PA1 (d) upon the host deasserting the DMA acknowledge, the receiver inputs the checksum then compares the send checksum to the receive checksum, any difference between the checksums indicating a data transfer error. PA1 (a) the sender accumulating each of the data words placed on the data lines into a partial send checksum; PA1 (b) the receiver accumulating each of the data words received from the data lines into a partial receive checksum; PA1 (c) upon the device suspending the data transfer by deasserting the DMA request before the data transfer is finished, the sender places the partial send checksum on the data lines; PA1 (d) upon the host deasserting the DMA acknowledge in response to the deassertion of the DMA request, the receiver inputs the partial send checksum, compares the partial send checksum to the partial receive checksum, any difference between the checksums indicating a data transfer error, and deasserting the DMA acknowledge, thereby indicating to the sender that the data transfer is complete, the sender subsequently zeroing the partial checksum so that, upon finally completing the data transfer, the partial checksum will be the sum of all data words in the data block. PA1 (a) the sender accumulating each data word placed on the data lines into a send checksum; PA1 (b) the receiver accumulating each data word received from the data lines into a receive checksum; PA1 (c) upon the host suspending the data transfer by deasserting the DMA acknowledge, the device relinquishing the data bus while continuing to assert the DMA request and the host and the device internally retaining the send and receive checksums; PA1 (d) upon the host resuming the data transfer by reasserting the DMA acknowledge, executing steps (a) through (d) until the last data word of the data block has been received by the receiver; PA1 (e) upon accumulating the last word sent by the sender into the receive checksum, the receiver comparing the send checksum to the receive checksum, any difference between the checksums indicating an error in the data transfer. This can continue repeatedly over multiple transfers if desired. PA1 (a) based on the difference between the parity words, the receiver determines words in error, the words in error being those of the data words erroneously transmitted between the sender and the receiver, and generates an error mask for each of the words in error; and PA1 (b) the receiver corrects the words in error by exclusively ORing (XORing) the words in error with the error masks. PA1 (a) fast-transfer-enabling circuitry driven by the write clock and read clock signals and connected to the write and read pipeline registers for enabling the write and read pipeline registers to input and output the data from and to the data bus on every edge of the write and read clock signals, respectively; PA1 (b) command control logic with inputs tied to a status input from the first command decoder and the data bus that asserts a READ COMMAND signal when the first command decoder asserts the COMMAND/STATUS signal and continuing to assert the READ COMMAND as long as data transfer has not been finished; and PA1 (c) a bus-enabling AND gate with two inputs tied respectively to the XFR ENA and the READ COMMAND signals, the output of the bus-enabling AND gate being an output enable (OE) signal that remains asserted as long as the data transfer is underway, the OE signal being tied to the output enable pin of the read pipeline register, thereby continually enabling the read pipeline register for output for low and high signal levels of the read clock signal.
For each of these methods, ATA-1 defined several modes of transfer, each mode defining a different transfer rate, the slowest being about 800 kilobytes/sec (mode 0), the fastest being about 8.33 megabytes/sec (mode 2).
In 1994, to provide faster hard drive data transfer rates, the second, and current, version of the ATA standard, ATA-2, was drafted, which, in addition to supporting the older modes, added new modes increasing the maximum transfer rate from 8.33 MB/sec to 16.6 MB/sec. While this represented a doubling in maximum data transfer rates, the new standard failed to remove the I/O bottleneck imposed by the ATA interface as modern disk drive devices and microprocessors are capable of transferring and using data at a much higher rates than 16.6 MB/sec. However, the ATA-2 standard could not support data transfer rates faster than 16.6 MB/sec due to the following limitations imposed by the physical and electrical interfaces and the interface protocol employed by the ATA standard:
The limited data transfer rate of the ATA interface was not a problem when I/O operations were performed solely over the slow, industry standard, or ISA, bus, on which data transfer rates could not exceed 8 MB/sec, and more commonly were held to 2 MB/sec. However, in modern microcomputer systems, I/O peripherals are often attached directly to a "local bus," by which is meant the microprocessor's native memory and control bus. In such a configuration, data can theoretically be transferred to and from peripherals at the full speed of the processor and memory subsystems, sometimes as fast as 100 MB/sec. Also contributing to the high data transfer rates possible over local busses is the fact that local busses are 32 bits wide as opposed to the 16 bit ISA bus and ATA standard.
To take full advantage of the local bus, system integrators have begun to ship computer systems with local bus adapters for disk drives, the adapters being capable of transferring data to the host at rates exceeding 40 MB/sec. However, given the current limitations of the ATA disk drive interface, there would be limited improvement in attaching an ATA disk drive to the local bus via one of these new adapters. Another challenge to such an implementation is that an ATA disk drive provides only 16 bits of data, not the 32 expected by the local bus and the host local bus adapter.
Consequently, there is a need for an ATA-compatible hard disk interface that is capable of transferring data at the fastest rate supported by the local bus adapters for disk drives. To be ATA-compatible, this interface should function with same physical cable and connectors, and cable lengths as in current ATA systems. This interface should also employ bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard; also, signal transitions seen on the cables should be no faster than those presently seen by current ATA devices.
Moreover, given that the target 40 MB/sec data transfer rate will push the physical limits of the ATA cables and connectors, which are already taxed at the current maximum transfer rates, there is a need for the new interface to provide data integrity checking and data correction for data words that could be corrupted during high-speed transmission. Of course, so that ATA backward compatibility is maintained, the data integrity checking feature must not require additional words in a data transfer, and the data correction feature must not require new data transfer protocols or additional data transfer overhead.
Finally, the need for full backward compatibility requires that a hard drive configured with the new, fast, error-correcting interface be transparently functional when it is plugged into a current ATA adapter provided by a legacy computer system, which is an existing or new computer system with ATA interfaces that comply with only the older versions of the ATA standard.